1. Field of the Invention
The present invention relates to a semiconductor integrated circuit to which a power supply voltage is supplied.
2. Description of the Related Art
On a semiconductor wafer, a plurality of semiconductor integrated circuit devices are formed in a matrix as semiconductor chips. In each of the plurality of semiconductor integrated circuits, an internal circuit for attaining a function and electrode pads connected to the internal circuit are formed. For example, after the semiconductor integrated circuit device is produced, an electrical characteristic test is performed on the internal circuit. At this time, if it is determined to be a good product in the electrical characteristic test, a dicing process for cutting the semiconductor integrated circuit devices away from the semiconductor wafer is performed.
The electrical characteristic test includes a probe test. In the probe test, probe needles of a probe card (probe) are pushed against the electrode pads of the semiconductor integrated circuit device, to measure the electric characteristics by using a tester or a storage oscilloscope.
FIG. 1 shows the configuration of a conventional semiconductor system 130 at the time of the probe test to which a semiconductor integrated circuit device 101 is applied. This semiconductor system 130 has a semiconductor integrated circuit device 101 and a probe. The semiconductor integrated circuit device 101 has an internal circuit 102, a plurality of power supply nodes 103-1 to 103-3, and a plurality of bonding pads 104-1 to 104-3. The plurality of power supply nodes 103-1 to 103-3 are connected to the internal circuit 102. The plurality of power supply nodes 103-1 to 103-3 are provided as separated power supplies to reduce mutual interference between noises caused by a high speed operation of the semiconductor integrated circuit device 101. Thus, a same power supply voltage V is applied to the plurality of power supply nodes 103-1 to 103-3. The plurality of bonding pads 104-1 to 104-3 are connected to the plurality of power supply nodes 103-1 to 103-3, respectively. At the time of the probe test, probe needles 131-1 to 131-3 of the probe are pushed to the plurality of bonding pads 104-1 to 104-3, respectively. The probe supplies the power supply voltage V through the probe needles 131-1 to 131-3 to the plurality of bonding pads 104-1 to 104-3, respectively.
In accordance with this electrical characteristic test, whether or not the semiconductor integrated circuit device 101 is good is determined. As a result, in case of a good product, the dicing process for cutting the semiconductor integrated circuit device 101 away from the semiconductor wafer is performed to make it as the product.
FIG. 2 shows the configuration of another semiconductor system 140 (in the state of the product) to which the semiconductor integrated circuit device 101 is applied. The conventional semiconductor system 140 has the semiconductor integrated circuit device 101, a plurality of bonding wires 141-1 to 141-3, and an external power supply 142. In the state of the product, the plurality of bonding wires 141-1 to 141-3 are connected to the plurality of bonding pads 104-1 to 104-3, respectively. The external power supply 142 is connected to the plurality of bonding wires 141-1 to 141-3. The external power supply 142 supplies the power supply voltage V through the plurality of bonding wires 141-1 to 141-3 to the plurality of bonding pads 104-1 to 104-3, respectively.
As mentioned above, the plurality of power supply nodes 103-1 to 103-3 are provided such that one power supply node is separated to reduce the mutual interference between the noises caused by the high speed operation of the semiconductor integrated circuit device 101, in the state of the product. However, at the time of the probe test, although the probe needles 131-1 to 131-3 are brought into contact with the plurality of bonding pads 104-1 to 104-3, respectively, the perfectly same power supply voltage V must be supplied to carry out the electrical characteristic test. The increase in the bonding pads provided in the semiconductor integrated circuit device 101 leads to the proportional increase in the probe needles to be brought into contact with them. Thus, there is a limit on the number of the probe needles that can be measured at one time in the electrical characteristic test. Also, since the probe needle is expensive, the increase in the probe needles to be used results in the increase in cost necessary for the electrical characteristic test. In this way, in the state of the product, it is desired to reduce the noise, and at the time of the probe test, it is desired to decrease the use of the probe needle.
In conjunction with the above description, Japanese Laid Open Patent Application (JP-P2002-245796A: a first conventional example) discloses a semiconductor device. This semiconductor device has a test mode and a usual mode. The semiconductor device has an internal circuit; a test circuit for outputting a control signal to the internal circuit in order to check the function of the internal circuit in the test mode; a first power supply line to supply a power supply current to the internal circuit from an external unit; and a second power supply line which is set to be active in the test mode to supply a second power supply current to the test circuit, and which is set to be inactive in the usual mode. Thus, the consumption current of a memory can be accurately measured without any influence of the consumption current of the test circuit that is used only at a time of an internal test.
Also, Japanese Laid Open Patent Application (JP-P2000-114324A: a second conventional example) discloses a probe card. The probe card is used in a test of a semiconductor device formed in a chip that has first and second pads adjacent to each other in a first direction. The probe card contains a first external circumference layer having first probe needles to be brought into contact with the first pads; and a second external circumference layer that is arranged above the first external circumference layer and has a second probe to be brought into contact with the second pads. The first and second external circumference layers are relatively movable along the first direction. Thus, it can be inspected even when an arrangement pattern of the pads and the chip size are changed.
Also, Japanese Laid Open Patent Application (JP-P2002-111007A: a third conventional example) discloses a semiconductor integrated circuit. The semiconductor integrated circuit includes a first power supply line for supplying a first voltage; a second power supply line for supplying a second voltage lower than the first voltage; a constant voltage generating circuit that is electrically connected to the first and second power supply lines; a third power supply line for supplying a constant voltage that is generated by the constant voltage generating circuit in which the first voltage is defined as a standard; and an operation circuit electrically connected to the first and third power supply lines. At least a part of transistors of the constant voltage generating circuit is formed from first field effect transistors of a partial depletion type having an SOI structure in which a body region and a source region are electrically connected and at least a part of the transistors of the operation circuit is formed from second field effect transistors of the partial depletion type having the SOI structure in which the body region is electrically in an floating state, and the threshold voltages of the first and second field effect transistors are equal. Thus, through the application based on the characteristics of the devices having the SOI structure, the super low power consumption is attained.
Also, Japanese Laid Open Patent Application (JP-A-Heisei 11-74357: a fourth conventional example) discloses an integrated circuit. The integrated circuit has a plurality of terminals. In the integrated circuit, a particular terminal or all of the terminals among the terminals are connected through a switching circuit including a selecting circuit to the power supply line and internal circuit in the integrated circuit, and each of the respective terminals is switched to a signal terminal or power supply terminal. Thus, the particular terminal or all the terminals can be used while their uses are changed to the power supply terminal or the signal terminal.